7nm SHA256 Mining & Computing Chip
second-generation SHA256 mining & computing chip C007 using TSMC’s 7nm FinFET process technology. Compared with the previous-generation 16nm chip C6, C007 has a higher integration density and improvements in circuit structure and low power consumption technology. The chip has further improved the computing power and energy consumption. C007 has 300 logical computing cores, and the single chip can achieve the computing power of 230GH/s and energy consumption ratio of 21W/TH, which is about 45% improvement in performance compared to the previous generation.
Core Voltage: ＜0.36V
Die Size: 12.7 mm²
Clock Speed: 780MHz
Chip Energy Consumption: 21W/TH
Technology Node: TSMC 7nm FinFet
In the ultra-low-voltage working mode, it supports minimum voltage of 0.28V and the power consumption can achieve 21W/TH;
The ultra-wide working voltage range in low-voltage working mode is 0.28V - 0.40V. It supports low-power mode, standard mode, large computing power mode and other operating modes. Users can configure different requirements of energy consumption ratio and computing power;
The working frequency can be continuously configured, up to 1GHz. The single-chip computing power can be dynamically adjusted from100GH/s to 300GH/s according to the application requirements;
It supports UART communication interface for command and data transmission, and the baud rate can be up to 12Mbps;
UART command supports CRC5 check protection, UART data supports CRC16 check protection;
It supports cascade of chips, and single link supports serial link of 255 chips.
Upgrade in Process Node
TSMC’s 7nm process is a new generation of process node. Compared with the 16nm FinFET process, the logic density of 7nm FinFET is about 1.7 times that of 16nm, the speed increases about 30% and the power consumption reduces about 60%, so as to achieve stronger performance and lower power consumption and heat generation.
Full Custom Design Methodology
fully customized design is reflected in the following four design procedures: 1) efficient system architecture design to match application scenarios; 2) RTL algorithm design to match optimal circuits; 3) cell library design with optimal energy consumption ratio and speed and 4) manual layout and wiring. The design process adopts customized design methods to obtain the best performance. Compared with automatic layout methods of other companies, the fully customized chips improve the performance by at least 10%.