6nm SHA256 Mining & Computing Chip
latest generation of SHA256 mining & computing chip, C006, has been officially released in the market. With advanced process technology and new low-power design, its performance has been greatly improved and its power consumption has reached a new low. C006 is the third-generation computing chip of . Compared with the 7 nm process technology, C006 is designed and produced with the advanced technology of TSMC 6nm FinFet process technology. The chip can work under low voltage below 0.36v and the minimum voltage can be down to 0.28v. The single chip has 360 logic calculation units, which achieves 280GH/s of computing power performance and 18W/TH of energy consumption ratio. Compared with the previous generation chip C007, there is about a 20% improvement in performance.
Core Voltage: ＜0.36V
Die Size: 12.6 mm²
Clock Speed: 780MHz
Chip Energy Consumption: 18W/TH
Technology Node: TSMC 6nm FinFet
Advanced 6nm Process Technology: with EUV lithography technology, the wavelength of the process light source is shortened to 13.5nm, the accuracy that is close to X-ray brings extremely high lithography resolution, which better balances the cost, performance and power consumption. Compared with the previous generation of 7nm, the density of 6nm transistors has increased by 18%, which allows more transistors to be integrated in the chip unit area, reduces chip power consumption by 8% and provide longer battery life.
Customized Cell Library: uses TSMC’s 6nm FinFET process technology, and the R&D team gave up using TSMC’s cell library and chose self-developed customized cell library according to product needs to achieve the optimal combination of area, power consumption and speed. By using customized standard cells, power consumption can be reduced by about 50%. At the same time, characterized standard cells, I/O and complex cells enable ASIC chips to operate at ultra-low voltages.
Manual Placement: the traditional design method uses EDA tools to automatically lay out, but full customization requires engineers to manually lay out thousands of unit devices to fully utilize the free space in the layout to achieve performance improvement.
Clock Optimization: contrary to the traditional design method, the fully customized design method requires that all computing units do not work at the same time, but select the off-peak execution to achieve a reduction in power consumption and an increase in speed.
Manual Gate-level Netlist: Unlike traditional design, full custom design requires logical design and physical design to be completed together. Front-end and back-end are designed together. When writing code in front-end, it’s better to understand the back-end design parameters in order to achieve the best optimization of area, power consumption and speed.