5nm SHA256 Mining & Computing Chip

is ready to launch the latest generation of SHA256 mining & computing chip–C005. The chip uses the most advanced process technology of TSMC 5nm FinFET and optimizes the high-performance low-power design method, so as to achieve the best energy efficiency ratio. Compared with the previous generation C006, the new generation C005 has obtained good improvements in area, speed and performance. C005 can work at a supply voltage below 0.36v, the minimum voltage can be down to 0.28v, and the single chip has 400 logic calculation units, which makes computing power achieve to 350GH/s and energy consumption ratio to 11W/TH. Compared with C006, there is about a 40% improvement in performance.


Version: C005

Algorithm: SHA256

Cores: 400

Core Voltage: <0.36V

Die Size: 9.1 mm²

Clock Speed: 850MHz

Performance: 350GH/s

Chip Energy Consumption: 11W/TH

Technology Node: TSMC 5nm FinFet


According to the estimate from the industry, TSMC’s 5nm FinFET may have the gate pitch of 48nm, the metal pitch of 30nm, the fin pitch of 25-26nm and the cell height is about 180nm. According to this data, the transistor density of TSMC’s 5nm will be 171.3 million Pcs per square millimeter. Compared with the first-generation 7nm process, the transistor density of 5nm has been increased by about 80%, which allows more transistors to be integrated in the unit area of the chip, reduces chip power consumption and provides longer battery life.

New Low Power Consumption: The latest generation chip C005 adopts low-power design architecture and unique low-power technologies. No matter what working modes, the advantage in power consumption is obvious, and reduction in the power consumption in some scenarios is expected to be 35%-40%.

Continuation of Full Custom Methodology: compared with the short design time and low coast of traditional standard cell method, the full custom design method can achieve the best performance, the smallest chip size and higher integration level. Although with higher design cost, more error prone and time consuming, in order to achieve the best performance, still continues to use and optimize the full custom method. uses its own designed cell library, manually compiles gate-level netlist and manual layout of resistance and capacitance according to its own library. According to the successful experience of previous generations of chips, the fully customized 5nm chip will be further optimized in power consumption and size.